1. Field of the Invention
The present invention relates to a metal oxide semiconductor (hereinafter, simply referred to as "MOS") logic circuit. More specifically, the present invention relates to a MOS logic circuit which has a reduced number of elements and a smaller circuit area, and may be operated with lower power consumption. The present invention further relates to a semiconductor apparatus incorporating such a MOS logic circuit.
2. Description of the Related Art
Recently, a pass-transistor logic circuit has been receiving much attention as a logic circuit. The pass-transistor logic circuit is advantageous over a complementary MOS (hereinafter, simply referred to as "CMOS") static circuit in view of its reduced number of transistors, i.e., elements, and its faster operation rate.
FIG. 8 is a circuit diagram showing an example of a conventional two-input AND (NAND) circuit which includes a pass-transistor logic circuit and a CMOS latch circuit 14. The pass-transistor logic circuit includes four NMOS (n-channel field effect MOS) transistors 11-1 to 11-4.
A two-input AND (NAND) circuit in general receives two input signals (e.g., signals A and B). However, the pass-transistor logic circuit shown in FIG. 8 requires four signals, i.e., signals A and B, and their respective inverted signals AX and BX. Each of the NMOS pass-transistors 11-1 to 11-4 passes a signal of logic "0" at a GND level, i.e., a "low" level (hereinafter, simply referred to as the "L level") without changing the voltage level of the signal. However, each of the NMOS pass-transistors 11-1 to 11-4 passes a signal of logic "1" at a VDD level (a power source voltage level), i.e., a "high" level (hereinafter, simply referred to as the "H level"), such that a voltage level of the signal is decreased by the threshold voltage level of the respective NMOS transistors 11-1 to 11-4. The CMOS latch circuit 14 is thus provided in order to recover the original "H" level and to enhance a load driving capability.
In order to pull up the "H" level to the VDD level, it is known, for example, to use a PMOS (p-channel field effect MOS) transistor as a pull-up element. FIG. 9 is a circuit diagram showing an example of such a conventional MOS logic circuit, which includes a pass-transistor logic circuit made from two NMOS transistors 11-1 and 11-2, and two PMOS transistors 12-1 and 12-2.
According to the conventional MOS logic circuit shown in FIG. 9, the NMOS transistor 11-1 is employed to perform a logic operation which is valid when an input signal is at the "H" level, while the PMOS transistor 12-1 is employed to perform a logic operation which is valid when an input signal is at the "L" level. Thus, no inverted signals are necessary.
An NMOS pass-transistor, i.e., the NMOS transistor 11-1, passes a signal at the "L" level without changing the voltage level thereof. However, with respect to a signal at the "H" level, the voltage level thereof is decreased by the threshold voltage level of the NMOS transistor 11-1. On the other hand, a PMOS pass-transistor, i.e., the PMOS transistor 12-1, passes a signal at the "H" level, while it passes a signal at the "L" level such thatthe voltage level thereof is increased by the threshold voltage level of the PMOS transistor 12-1.
Therefore, in the MOS logic circuit shown in FIG. 9, the PMOS transistor 12-2 is provided for pulling up an output of the pass-transistor logic circuit to the VDD level. Similarly, the NMOS transistor 11-2 is provided for pulling down an output of the pass-transistor logic circuit to the GND level. Referring to FIG. 9, the circuit further includes an inverter 13.
Furthermore, FIG. 10B is a circuit diagram showing a conventional logic circuit using inverted input signals. FIG. 10A is a circuit diagram showing a conventional CMOS circuit having an improved configuration over the logic circuit shown in FIG. 10B, which is realized without using inverted input signals.
As can be appreciated by comparing FIGS. 10A and 10B, the CMOS circuit shown in FIG. 10A does not require inverters 13-1 and 13-2 used in the logic circuit shown in FIG. 10B. Moreover, the inverted input signals AX and BX are not necessary in the CMOS circuit shown in FIG. 10A. As a result, the wiring area of the CMOS circuit shown in FIG. 10A is reduced. However, as described above, an output at the "H" level is decreased by the threshold voltage of each of the respective NMOS transistors 11-1 to 11-4 while an output at the "L" level is increased by the threshold voltage level of each of the respective PMOS transistors 12-1 to 12-4.
The conventional pass-transistor logic circuit shown in FIG. 8 is advantageous over a CMOS static circuit in view of its reduced number of transistors as described above. However, it has the following disadvantages.
(1) Since the pass-transistor logic circuit shown in FIG. 8 requires inverted signals, the number of signals required is doubled compared to that required in the CMOS static circuit. As a result, the number of signal lines is increased, resulting in the enlarged wiring area.
(2) The doubled number of signal lines leads to the doubled number of signal transitions (i.e., signal alternations) between the "H" and "L" levels. As a result, the amount of current required for charging and discharging the wiring capacitance is increased, resulting in an increased amount of power consumption.
(3) During a transition period where levels of positive and negative signals alternate, there may be a moment when both of the positive and negative signals are at the "H" level. In such a state, the NMOS transistor is turned on, which causes a direct current path to be produced between the VDD level and the GND level in the pass-transistor logic circuit, through which a penetrating current flows.
(4) The "H" level output from the pass-transistor logic circuit is decreased from the VDD level by the threshold voltage Vthn of the NMOS transistor. When this voltage VDD-Vthn is applied to a gate of a PMOS transistor of the CMOS latch circuit 14 where the threshold voltage Vthp of the PMOS transistor is such that Vthn&gt;.vertline.Vthp.vertline., the PMOS transistor turns on so that the voltage VDD-Vthn is applied to a gate of the NMOS transistor. As a result, a penetrating current flows between the VDD level and the GND level via the NMOS transistor in the ON state, until the CMOS latch circuit 14 is inverted.
Furthermore, the logic circuit shown in FIG. 9 has disadvantages regarding a penetrating current flowing through the circuit whenever the level of output alternates. This is due to the following reason.
As described above, the CMOS latch 12, i.e., the PMOS transistor 12-2 and the NMOS transistor 11-2, is provided in order to increase the potential at the "H" level of the output Y1 to the VDD level, and to decrease the potential at the "L" level of the output Y1 to the GND level. Under such a situation, in the case where the NMOS transistor 11-1 is turned on and signal B at the "H" level is supplied as the output Y1, the "H" level is decreased by the threshold voltage level of the NMOS transistor 11-1. A potential of the output Y1 is determined based on a ratio of the "H" level derived from the signal B through the NMOS transistor 11-1 and the "L" level derived from the GND level through the turned-on NMOS transistor 11-2. Therefore, the impedance of the NMOS transistor 11-2 is set at such a high level that the potential of the output Y1 is higher than the inverting voltage of the inverter 13 of the CMOS latch 12 when the signal B at the "H" level is supplied as the output Y1 by the turned-on NMOS transistor 11-1.
Thus, when the potential of the output Y1 at the "H" level exceeds the inverting voltage of the inverter 13, the output Y2 of the inverter 13 becomes at the "L" level. When the output Y2 becomes at the "L" level, the NMOS transistor 11-2 is turned off while the PMOS transistor 12-2 is turned on. Since the NMOS transistor 11-2 is turned off, a direct current path running from a point, where the signal B is input, to the GND level via the NMOS transistor 11-1 and the NMOS transistor 11-2 is blocked, whereby no penetrating current flows therethrough. On the other hand, since the PMOS transistor 12-2 is turned on, the "H" level of the output Y1 is increased to the VDD level.
When the PMOS transistor 12-1 is turned on and the signal A at the "L" level is provided as the output Y1, the "L" level is increased from the GND level by the threshold voltage of the PMOS transistor 12-1. The potential of the output Y1 is determined based on a ratio of the "L" level derived from the GND level through the PMOS transistor 12-1 and the "H" level derived from the VDD level through the PMOS transistor 12-2. Therefore, the impedance of the PMOS transistor 12-2 is set at such a high level that the potential of the output Y1 is lower than the inverting voltage of the inverter 13 of the CMOS latch 12 when the signal A at the "L" level is supplied as the output Y1 by the turned-on PMOS transistor 12-1. Thus, when the output Y1 alternates from the "H" level to the "L" level, and the potential of the output Y1 becomes lower than the inverting voltage of the inverter 13, the output Y2 from the inverter 13 inverts to the "H" level. When the output Y2 becomes at the "H" level, the PMOS transistor 12-2 is turned off while the NMOS transistor 11-2 is turned on. Since the PMOS transistor 12-2 is turned off, a direct current path running from the GND level to the VDD level via the PMOS transistor 12-1 and the PMOS transistor 12-2 is blocked, whereby no penetrating current flows therethrough. Since the NMOS transistor 11-2 is turned on, the "L" level of the output Y2 is pulled down to the GND level. However, both of the NMOS and PMOS transistors of the inverter 13 remain in the ON state until the inverter 13 is inverted, whereby a penetrating current flows between the VDD level and the GND level via the inverter 13.
Thus, the logic circuit shown in FIG. 9 has a problem of a penetrating current flowing therethrough as described above.
Recently, a technology for reducing power consumption of LSIs (Large Scale Integrated circuits) is receiving attention. In order to realize low power consumption, it is effective to provide circuits which can be operated at a lower voltage. The threshold voltage of the transistor needs to be low in order to allow a pass-transistor logic circuit to be operated at a low voltage.
FIG. 11 is a circuit diagram showing an exemplary logic circuit.
Herein, the threshold voltage of a NMOS transistor is assumed to be Vthn and the threshold voltage of a PMOS transistor is assumed to be Vthp. When inputs (A, B, C, AX, BX, CX) change from (1, 0, 0, 0, 1, 1) to (1, 1, 0, 0, 0, 1) in the logic circuit shown in FIG. 11, a potential of output Y1 changes from 0 V to VDD-Vthn. The voltage VDD-Vthn needs to exceed the threshold voltage Vthn of an NMOS transistor of the CMOS latch 12.
For realizing the above, the following relationship (1) needs to be satisfied: EQU VDD-Vthn&gt;Vthn (1)
which can be simplified as:
VDD&gt;2Vthn (2)
According to the above relationship (2), for example, when Vthn is 0.6 V, the circuit cannot be operated with VDD of 1.2 V or less.
In the logic circuit shown in FIG. 9, the "L" level is increased by the threshold voltage Vthp of the PMOS transistor. Thus, the following relationship (3) needs to be satisfied at the same time: EQU VDD&gt;2Vthn,VDD&gt;2.vertline.Vthp.vertline. (3)
When the number of the stacked pass-transistors is increased, the apparent threshold voltage becomes larger due to a back gate effect, and thus, the VDD level needs to be higher. Alternatively, the number of the stacked pass-transistors needs to be as small as two, so that the VDD level does not become high, resulting in the disadvantage of an increased number of amplifiers.
In order for the logic circuit to be operated with VDD=1 V so as to reduce power consumption, Vthn and .vertline.Vthp.vertline. need to be equal to or lower than about 0.3 V, considering variations in the threshold voltage Vthn. However, when the threshold voltage is as low as about 0.3 V, the amount of leakage current generated upon turning off of the transistor becomes large, which undesirably increases the amount of a penetrating current.
For the above-described reasons, it is desirable to provide a logic circuit requiring a smaller number of elements and providing a smaller circuit area, and which may be operated with lower power consumption.